One of the foremost semiconductor technologies is the CMOS technology, and especially the Silicon Gate CMOS Technology. The most common way to implement this technology is to use N+ doped polycrystalline silicon for the gate electrode of both the N-Channel device and P-Channel device. Use of the N+ doped material for the gate electrode of the P-Channel device, however, requires counter doping of the channel region of that device in order to adjust the threshold voltage to a low enough value to be useful in most circuits. The resulting P-Channel device is known as a buried channel device.
As the physical dimensions of the MOS transistor continue to be reduced in order to meet the requirements for submicron and even sub-half micron CMOS technologies, the use of N+ doped poly crystalline silicon as the gate electrode for the P-Channel device begins to cause serious problems. The resulting P-Channel device suffers from seriously degraded short channel behavior because of the presence of the buried channel. Alternate technologies have been advanced to overcome this problem, such as using mid-gap refractory gate electrodes, dual N+/P+ polycrystalline silicon gate electrodes, or modified polycrystalline silicon gate work function using polycrystalline silicon doped with germanium, and the like. Although these alternate process technologies result in useful transistor designs, the N+ polycrystalline silicon gate electrode process continues to be the favored process because of its relative process simplicity and maturity. The favored process requires a shallow doped region of carefully controlled dopant concentration to achieve a device having a desired and controllable threshold voltage. Attempts to achieve such a shallow doped region have included the use of amorphizing implants before channel doping and implantation of BF.sub.2 through the gate oxide. The former causes damage to the substrate in the channel region which can adversely affect transistor characteristics because of mobility degradation and the increase in surface state density. The latter cause gate oxide and hot carrier reliability problems.
Accordingly, a need existed for an improved process for fabricating semiconductor devices which would overcome the deficiencies of the prior art process technologies and still maintain the processing simplicity of the N+ polycrystalline silicon gate process.